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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ad9752* one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 1999 12-bit, 125 msps high performance txdac ? d/a converter functional block diagram 150pf +1.20v ref avdd acom reflo icomp current source array +5v segmented switches lsb switches refio fs adj dvdd dcom clock +5v r set 0.1 m f clock iouta ioutb 0.1 m f latches ad9752 sleep digital data inputs (db11Cdb0) features high performance member of pin-compatible txdac product family 125 msps update rate 12-bit resolution excellent spurious free dynamic range performance sfdr to nyquist @ 5 mhz output: 79 dbc differential current outputs: 2 ma to 20 ma power dissipation: 185 mw @ 5 v power-down mode: 20 mw @ 5 v on-chip 1.20 v reference cmos-compatible +2.7 v to +5.5 v digital interface package: 28-lead soic and tssop edge-triggered latches applications wideband communication transmit channel: direct if basestations wireless local loop digital radio link direct digital synthesis (dds) instrumentation product description the ad9752 is a 12-bit resolution, wideband, second generation member of the txdac series of high performance, low p ower cmos digital-to-analog-converters (dacs). the txdac family, which consists of pin compatible 8-, 10-, 12-, and 14-bit dacs, is specifically optimized for the transmit signal path of communica- tion systems. all of the devices share the same interface options, small outline package and pinout, thus providing an upward or downward component selection path based on performance, resolution and cost. the ad9752 offers exceptional ac and dc performance while supporting update rates up to 125 msps. the ad9752s flexible single-supply operating range of 4.5 v to 5.5 v and low power dissipation are well suited for portable and low power applications. its power dissipation can be further reduced to a mere 65 mw, without a significant degradation in performance, by lowering the full-scale current output. also, a power-down mode reduces the standby power dissipation to approximately 20 mw. the ad9752 is manufactured on an advanced cmos process. a segmented current source architecture is combined with a proprietary switching technique to reduce spurious components and enhance dynamic performance. edge-triggered input latches and a 1.2 v temperature compensated bandgap reference have been integrated to provide a complete monolithic dac solution. the digital inputs support +2.7 v to +5 v cmos logic families. the ad9752 is a current-output dac with a nominal full-scale output current of 20 ma and > 100 k w output impedance. differential current outputs are provided to support single- ended or differential applications. matching between the two current outputs ensures enhanced dynamic performance in a differential output configuration. the current outputs may be tied directly to an output resistor to provide two complemen- tary, single-ended voltage outputs or fed directly into a trans- former. the output voltage compliance range is 1.25 v. the on-chip reference and control amplifier are configured for maximum accuracy and flexibility. the ad9752 can be driven by the on-chip reference or by a variety of external reference voltages. the internal control amplifier, which provides a wide (>10:1) adjustment span, allows the ad9752 full-scale current to be adjusted over a 2 ma to 20 ma range while maintaining excellent dynamic performance. thus, the ad9752 may oper- ate at reduced power levels or be adjusted over a 20 db range to provide additional gain ranging capabilities. the ad9752 is available in 28-lead soic and tssop packages. it is specified for operation over the industrial temperature range. product highlights 1. the ad9752 is a member of the wideband txdac product family that provides an upward or downward component selec- tion path based on resolution (8 to 14 bits), performance and cost. the entire family of txdacs is available in industry standard pinouts. 2. manufactured on a cmos process, the ad9752 uses a proprietary switching technique that enhances dynamic performance beyond that previously attainable by higher power/cost bipolar or bicmos devices. 3. on-chip, edge-triggered input cmos latches interface readily to +2.7 v to +5 v cmos logic families. the ad9752 can support update rates up to 125 msps. 4. a flexible single-supply operating range of 4.5 v to 5.5 v and a wide full-scale current adjustment span of 2 ma to 20 ma allow the ad9752 to operate at reduced power levels. 5. the current output(s) of the ad9752 can be easily config- ured for various single-ended or differential circuit topologies. txdac is a registered trademark of analog devices, inc. *protected by u.s. patents numbers 5450084, 5568145, 5689257, 5612697 and 5703519. other patents pending.
C2C ad9752Cspecifications rev. 0 (t min to t max , avdd = +5 v, dvdd = +5 v, i outfs = 20 ma, unless otherwise noted) dc specifications parameter min typ max units resolution 12 bits dc accuracy 1 integral linearity error (inl) t a = +25 c C1.5 0.5 +1.5 lsb t min to t max C2.0 +2.0 lsb differential nonlinearity (dnl) t a = +25 c C0.75 0.25 +0.75 lsb t min to t max C1.0 +1.0 lsb analog output offset error C0.02 +0.02 % of fsr gain error (without internal reference) C2 0.5 +2 % of fsr gain error (with internal reference) C5 1.5 +5 % of fsr full-scale output current 2 2.0 20.0 ma output compliance range C1.0 1.25 v output resistance 100 k w output capacitance 5 pf reference output reference voltage 1.14 1.20 1.26 v reference output current 3 100 na reference input input compliance range 0.1 1.25 v reference input resistance 1 m w small signal bandwidth 0.5 mhz temperature coefficients offset drift 0 ppm of fsr/ c gain drift (without internal reference) 50 ppm of fsr/ c gain drift (with internal reference) 100 ppm of fsr/ c reference voltage drift 50 ppm/ c power supply supply voltages avdd 4.5 5.0 5.5 v dvdd 2.7 5.0 5.5 v analog supply current (i avdd ) 4 34 39 ma digital supply current (i dvdd ) 5 35ma supply current sleep mode (i avdd ) 6 48ma power dissipation 5 (5 v, i outfs = 20 ma) 185 220 mw power supply rejection ratio 7 avdd C0.4 +0.4 % of fsr/v power supply rejection ratio 7 dvdd C0.025 +0.025 % of fsr/v operating range C40 +85 c notes 1 measured at iouta, driving a virtual ground. 2 nominal full-scale current, i outfs , is 32 the i ref current. 3 use an external buffer amplifier to drive any external load. 4 requires +5 v supply. 5 measured at f clock = 25 msps and i out = static full scale (20 ma). 6 logic level for sleep pin must be referenced to avdd. min v ih = 3.5 v. 7 5% power supply variation. specifications subject to change without notice.
rev. 0 C3C ad9752 dynamic specifications parameter min typ max units dynamic performance maximum output update rate (f clock ) 125 msps output settling time (t st ) (to 0.1%) 1 35 ns output propagation delay (t pd )1ns glitch impulse 5 pv-s output rise time (10% to 90%) 1 2.5 ns output fall time (10% to 90%) 1 2.5 ns output noise (i outfs = 20 ma) 50 pa/ ? hz output noise (i outfs = 2 ma) 30 pa/ ? hz ac linearity spurious-free dynamic range to nyquist f clock = 25 msps; f out = 1.00 mhz 0 dbfs output t a = +25 c 75 84 dbc C6 dbfs output 76 dbc C12 dbfs output 81 dbc f clock = 50 msps; f out = 1.00 mhz 81 dbc f clock = 50 msps; f out = 2.51 mhz 81 dbc f clock = 50 msps; f out = 5.02 mhz 76 dbc f clock = 50 msps; f out = 14.02 mhz 62 dbc f clock = 50 msps; f out = 20.2 mhz 60 dbc f clock = 100 msps; f out = 2.5 mhz 78 dbc f clock = 100 msps; f out = 5 mhz 76 dbc f clock = 100 msps; f out = 20 mhz 63 dbc f clock = 100 msps; f out = 40 mhz 55 dbc spurious-free dynamic range within a window f clock = 25 msps; f out = 1.00 mhz 84 93 dbc f clock = 50 msps; f out = 5.02 mhz; 2 mhz span 86 dbc f clock = 100 msps; f out = 5.04 mhz; 4 mhz span 86 dbc total harmonic distortion f clock = 25 msps; f out = 1.00 mhz t a = +25 c C82 C74 dbc f clock = 50 mhz; f out = 2.00 mhz C76 dbc f clock = 100 mhz; f out = 2.00 mhz C76 dbc multitone power ratio (8 tones at 110 khz spacing) f clock = 20 msps; f out = 2.00 mhz to 2.99 mhz 0 dbfs output 81 dbc C6 dbfs output 81 dbc C12 dbfs output 85 dbc C18 dbfs output 86 dbc notes 1 measured single ended into 50 w load. specifications subject to change without notice. (t min to t max , avdd = +5 v, dvdd = +5 v, i outfs = 20 ma, differential tran sformer coupled output, 50 v doubly terminated, unless otherwise noted)
rev. 0 ad9752 C4C caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad9752 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings* with parameter respect to min max units avdd acom C0.3 +6.5 v dvdd dcom C0.3 +6.5 v acom dcom C0.3 +0.3 v avdd dvdd C6.5 +6.5 v clock, sleep dcom C0.3 dvdd + 0.3 v digital inputs dcom C0.3 dvdd + 0.3 v iouta, ioutb acom C1.0 avdd + 0.3 v icomp acom C0.3 avdd + 0.3 v refio, fsadj acom C0.3 avdd + 0.3 v reflo acom C0.3 +0.3 v junction temperature +150 c storage temperature C65 +150 c lead temperature (10 sec) +300 c *stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum ratings for extended periods may effect device reliability. digital specifications parameter min typ max units digital inputs logic 1 voltage @ dvdd = +5 v 1 3.5 5 v logic 1 voltage @ dvdd = +3 v 2.1 3 v logic 0 voltage @ dvdd = +5 v 1 0 1.3 v logic 0 voltage @ dvdd = +3 v 0 0.9 v logic 1 current C10 +10 m a logic 0 current C10 +10 m a input capacitance 5 pf input setup time (t s ) 2.0 ns input hold time (t h ) 1.5 ns latch pulsewidth (t lpw ) 3.5 ns notes 1 when dvdd = +5 v and logic 1 voltage ? 3.5 v and logic 0 voltage ? 1.3 v. ivdd can increase by up to 10 ma, depending on f clock . specifications subject to change without notice. 0.1% 0.1% t s t h t lpw t pd t st db0Cdb11 clock iouta or ioutb figure 1. timing diagram (t min to t max , avdd = +5 v, dvdd = +5 v, i outfs = 20 ma, unless otherwise noted) ordering guide temperature package package model range description options* ad9752ar C40 c to +85 c 28-lead 300 mil soic r-28 ad9752aru C40 c to +85 c 28-lead tssop ru-28 AD9752-EB evaluation board *r = small outline ic; ru = thin shrink small outline package. thermal characteristics thermal resistance 28-lead 300 mil soic q ja = 71.4 c/w q jc = 23 c/w 28-lead tssop q ja = 97.9 c/w q jc = 14.0 c/w
rev. 0 ad9752 C5C pin configuration 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 top view (not to scale) 28 27 26 25 24 23 22 21 ad9752 nc = no connect (msb) db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 nc nc clock dvdd dcom nc avdd icomp iouta ioutb acom nc fs adj refio reflo sleep pin function descriptions pin no. name description 1 db11 most significant data bit (msb). 2C11 db10Cdb1 data bits 1C10. 12 db0 least significant data bit (lsb). 13, 14, 19, 25 nc no internal connection. 15 sleep power-down control input. active high. contains active pull-down circuit, thus may be left u nterminated if not used. 16 reflo reference ground when internal 1.2 v reference used. connect to avdd to disable internal reference. 17 refio reference input/output. serves as reference input when internal reference disabled (i.e., tie reflo to avdd). serves as 1.2 v reference output when internal reference activated (i.e., tie reflo to acom). requires 0.1 m f capacitor to acom when internal reference activated. 18 fs adj full-scale current output adjust. 19 nc no connect. 20 acom analog common. 21 ioutb complementary dac current output. full-scale current when all data bits are 0s. 22 iouta dac current output. full-scale current when all data bits are 1s. 23 icomp internal bias node for switch driver circuitry. decouple to acom with 0.1 m f capacitor. 24 avdd analog supply voltage (+4.5 v to +5.5 v). 26 dcom digital common. 27 dvdd digital supply voltage (+2.7 v to +5.5 v). 28 clock clock input. data latched on positive edge of clock.
rev. 0 ad9752 C6C definitions of specifications linearity error (also called integral nonlinearity or inl) linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. differential nonlinearity (or dnl) dnl is the measure of the variation in analog value, normalized to full scale, associated with a 1 lsb change in digital input code. monotonicity a d/a converter is monotonic if the output either increases or remains constant as the digital input increases. offset error the deviation of the output current from the ideal of zero is called offset error. for iouta, 0 ma output is expected when the inputs are all 0s. for ioutb, 0 ma output is expected when all inputs are set to 1s. gain error the difference between the actual and ideal output span. the actual span is determined by the output when all inputs are set to 1s minus the output when all inputs are set to 0s. output compliance range the range of allowable voltage at the output of a current-output dac. operation beyond the maximum compliance limits may cause either output stage saturation or breakdown resulting in nonlinear performance. temperature drift temperature drift is specified as the maximum change from the ambient (+25 c) value to the value at either t min or t max . for offset and gain drift, the drift is reported in ppm of full-scale range (fsr) per c. for reference drift, the drift is reported in ppm per c. power supply rejection the maximum change in the full-scale output as the supplies are varied from nominal to minimum and maximum specified voltages. settling time the time required for the output to reach and remain within a specified error band about its final value, measured from the start of the output transition. glitch impulse asymmetrical switching times in a dac give rise to undesired output transients that are quantified by a glitch impulse. it is specified as the net area of the glitch in pv-s. spurious-free dynamic range the difference, in db, between the rms amplitude of the output signal and the peak spurious signal over the specified bandwidth. total harmonic distortion thd is the ratio of the rms sum of the first six harmonic components to the rms value of the measured input signal. it is expressed as a percentage or in decibels (db). multitone power ratio the spurious-free dynamic range for an output containing mul- tiple carrier tones of equal amplitude. it is measured as the difference between the rms amplitude of a carrier tone to the peak spurious signal in the region of a removed tone. +1.20v ref avdd acom reflo icomp pmos current source array +5v segmented switches for db11Cdb3 lsb switches refio fs adj dvdd dcom clock +5v r set 2k v 0.1 m f dvdd dcom iouta ioutb 0.1 m f ad9752 sleep 50 v retimed clock output* latches digital data tektronix awg-2021 w/option 4 lecroy 9210 pulse generator clock output 50 v 20pf 50 v 20pf 100 v to hp3589a spectrum/ network analyzer 50 v input mini-circuits t1-1t * awg2021 clock retimed such that digital data transitions on falling edge of 50% duty cycle clock. 150pf figure 2. basic ac characterization test setup
rev. 0 ad9752 C7C typical ac characterization curves @ +5 v supplies (avdd = +5 v, dvdd = +5 v, i outfs = 20 ma, 50 v doubly terminated load, differential output, t a = +25 8 c, sfdr up to nyquist, u nless otherwise noted) f out C mhz sfdr C db 90 80 40 0 1 100 10 70 60 50 25msps 50msps 125msps 65msps figure 3. sfdr vs. f out @ 0 dbfs f out C mhz sfdr C dbc 90 80 40 0 530 20 70 60 50 10 15 25 C12dbfs C6dbfs 0dbfs figure 6. sfdr vs. f out @ 65 msps a out C dbfs sfdr C db 90 70 C30 C25 0 C10 80 C20 C15 C5 40 60 50 2.27mhz@25msps 4.55mhz@50msps 5.91mhz@65msps 11.36mhz@125msps figure 9. single-tone sfdr vs. a out @ f out = f clock /11 sfdr C db 90 80 40 0 214 12 70 60 50 46 810 C12dbfs 0dbfs C6dbfs f out C mhz figure 4. sfdr vs. f out @ 25 msps sfdr C db 90 80 40 0 10 60 40 70 60 50 20 30 50 C6dbfs 0dbfs C12dbfs f out C mhz figure 7. sfdr vs. f out @ 125 msps a out C dbfs sfdr C db 90 70 C30 C25 0 C10 80 C20 C15 C5 40 60 50 5mhz@25msps 10mhz@50msps 13mhz@65msps 25mhz@125msps figure 10. single-tone sfdr vs. a out @ f out = f clock /5 f out C mhz sfdr C dbc 90 80 40 05 25 10 70 60 50 15 20 C12dbfs C6dbfs 0dbfs figure 5. sfdr vs. f out @ 50 msps f out C mhz sfdr C dbc 90 0 212 8 80 70 46 10 50 60 10ma fs 20ma fs 5ma fs figure 8. sfdr vs. f out and i outfs @ 25 msps and 0 dbfs f clock C msps snr C db 0 20 120 80 80 40 60 100 60 70 50 20ma fs 10ma fs 5ma fs figure 11. snr vs. f clock and i outfs @ f out = 2 mhz and 0 dbfs
rev. 0 ad9752 C8C code error C lsb 0 4000 1000 2000 3000 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 C0.1 C0.2 C0.3 C0.4 figure 12. typical inl f out C mhz signal amplitude C dbm 0 60 10 20 30 0 C10 C20 C30 C40 C100 C50 C60 C70 C80 C90 40 50 f clk = 125msps f out1 = 13.5mhz f out2 = 14.5mhz a out = 0dbfs sfdr = 68.4dbc figure 15. dual-tone sfdr code error C lsb 0 4000 1000 2000 3000 0.1 0.0 C0.1 C0.2 C0.3 C0.5 C0.4 figure 13. typical dnl signal amplitude C dbm 0 30.0 5.0 10.0 15.0 0 C10 C20 C30 C40 C100 C50 C60 C70 C80 C90 20.0 25.0 f clk = 65msps f out1 = 6.25mhz f out2 = 6.75mhz f out3 = 7.25mhz f out4 = 7.75mhz sfdr = 69dbc amplitude = 0dbfs f out C mhz figure 16. four-tone sfdr temperature C 8 c sfdr C dbc C55 95 C30 C5 20 90 70 80 50 60 45 70 f out = 4mhz f out = 10mhz f out = 29mhz f out = 40mhz figure 14. sfdr vs. temperature @ 125 msps, 0 dbfs
rev. 0 ad9752 C9C functional description figure 17 shows a simplified block diagram of the ad9752. the ad9752 consists of a large pmos current source array that is capable of providing up to 20 ma of total current. the array is divided into 31 equal currents that make up the five most significant bits (msbs). the next four bits or middle bits consist of 15 equal current sources whose value is 1/16th of an msb current source. the remaining lsbs are binary weighted frac- tions of the middle-bits current sources. implementing the middle and lower bits with current sources, instead of an r-2r ladder, enhances its dynamic performance for multitone or low amplitude signals and helps maintain the dacs high output impedance (i.e., >100 k w ). all of these current sources are switched to one or the other of the two output nodes (i.e., iouta or ioutb) via pmos differential current switches. the switches are based on a new architecture that drastically improves distortion performance. this new switch architecture reduces various timing errors and provides matching complementary drive signals to the inputs of the differential current switches. the analog and digital sections of the ad9752 have separate power supply inputs (i.e., avdd and dvdd). the digital section, which is capable of operating up to a 125 msps clock rate and over a +2.7 v to +5.5 v operating range, consists of edge-triggered latches and segment decoding logic circuitry. the analog section, which can operate over a +4.5 v to +5.5 v range, includes the pmos current sources, the associated differ- ential switches, a 1.20 v bandgap voltage reference and a refer- ence control amplifier. the full-scale output current is regulated by the reference con- trol amplifier and can be set from 2 ma to 20 ma via an exter- nal resistor, r set . the external resistor, in combination with both the reference control amplifier and voltage reference v refio , sets the reference current i ref , which is mirrored over to the segmented current sources with the proper scaling factor. the full-scale current, i outfs , is thirty-two times the value of i ref . dac transfer function the ad9752 provides complementary current outputs, iouta and ioutb. iouta will provide a near full-scale current output, i outfs , when all bits are high (i.e., dac code = 4095) while ioutb, the complementary output, provides no current. the current output appearing at iouta and ioutb is a function of both the input code and i outfs and can be expressed as: iouta = ( dac code /4096) i outfs (1) ioutb = (4095 C dac code )/4096 i outfs (2) where dac code = 0 to 4095 (i.e., decimal representation). as mentioned previously, i outfs is a function of the reference current i ref , which is nominally set by a reference voltage v refio and external resistor r set . it can be expressed as: i outfs = 32 i ref (3) where i ref = v refio / r set (4) the two current outputs will typically drive a resistive load directly or via a transformer. if dc coupling is required, iouta and ioutb should be directly connected to matching resistive loads, r load , which are tied to analog common, acom. note, r load may represent the equivalent load resistance seen by iouta or ioutb as would be the case in a doubly terminated 50 w or 75 w cable. the single-ended voltage output appearing at the iouta and ioutb nodes is simply : v outa = iouta r load (5) v outb = ioutb r load (6) note the full-scale value of v outa and v outb should not exceed the specified output compliance range to maintain specified distortion and linearity performance. the differential voltage, v diff , appearing across iouta and ioutb is: v diff = ( iouta C ioutb ) r load (7) substituting the values of i outa , i outb , and i ref ; v diff can be expressed as: v diff = {(2 dac code C 4095)/4096} (32 r load / r set ) v refio (8) these last two equations highlight some of the advantages of operating the ad9752 differentially. first, the differential op- eration will help cancel common-mode error sources associated with i outa and i outb such as noise, distortion and dc offsets. second, the differential code dependent current and subsequent voltage, v diff , is twice the value of the single-ended voltage output (i.e., v outa or v outb ), thus providing twice the signal power to the load. note, the gain drift temperature performance for a single-ended (v outa and v outb ) or differential output (v diff ) of the ad9752 can be enhanced by selecting temperature tracking resistors for r load and r set due to their ratiometric relationship as shown in equation 8. digital data inputs (db11Cdb0) 150pf +1.20v ref avdd acom reflo icomp pmos current source array +5v segmented switches for db11Cdb3 lsb switches refio fs adj dvdd dcom clock +5v r set 2k v 0.1 m f iouta ioutb 0.1 m f ad9752 sleep latches i ref v refio clock i outb i outa r load 50 v v outb v outa r load 50 v v diff = v outa C v outb figure 17. functional block diagram
rev. 0 ad9752 C10C reference operation the ad9752 contains an internal 1.20 v bandgap reference that can easily be disabled and overridden by an external refer- ence. refio serves as either an input or output depending on whether the internal or an external reference is selected. if reflo is tied to acom, as shown in figure 18, the internal reference is activated and refio provides a 1.20 v output. in this case, the internal reference must be compensated externally with a ceramic chip capacitor of 0.1 m f or greater from refio to reflo. also, refio should be buffered with an external amplifier having an input bias current less than 100 na if any additional loading is required. 150pf +1.2v ref avdd reflo current source array +5v refio fs adj 2k v 0.1 m f ad9752 additional load optional external ref buffer figure 18. internal reference configuration the internal reference can be disabled by connecting reflo to avdd. in this case, an external reference may then be applied to refio as shown in figure 19. the external reference may provide either a fixed reference voltage to enhance accuracy and drift performance or a varying reference voltage for gain control. note that the 0.1 m f compensation capacitor is not required since the internal reference is disabled, and the high input im- pedance (i.e., 1 m w ) of refio minimizes any loading of the external reference. 150pf +1.2v ref avdd reflo current source array avdd refio fs adj r set ad9752 external ref i ref = v refio /r set avdd reference control amplifier v refio figure 19. external reference configuration reference control amplifier the ad9752 also contains an internal control amplifier that is used to regulate the dacs full-scale output current, i outfs . the control amplifier is configured as a v-i converter as shown in figure 19, such that its current output, i ref , is determined by the ratio of the v refio and an external resistor, r set , as stated in equation 4. i ref is copied over to the segmented current sources with the proper scaling factor to set i outfs as stated in equation 3. the control amplifier allows a wide (10:1) adjustment span of i outfs over a 2 ma to 20 ma range by setting iref between 62.5 m a and 625 m a. the wide adjustment span of i outfs provides several application benefits. the first benefit relates directly to the power dissipation of the ad9752, which is proportional to i outfs (refer to the power dissipation section). the second benefit relates to the 20 db adjustment, which is useful for system gain control purposes. the small signal bandwidth of the reference control amplifier is approximately 0.5 mhz. the output of the control amplifier is internally compensated via a 150 pf capacitor that limits the control amplifier small-signal bandwidth and reduces its output impedance. since the C3 db bandwidth corresponds to the dominant pole, and hence the time constant, the settling time of the control amplifier to a stepped reference input re- sponse can be approximated. in this case, the time constant can be approximated to be 320 ns. there are two methods in which i ref can be varied for a fixed r set . the first method is suitable for a single-supply system in which the internal reference is disabled, and the common-mode voltage of refio is varied over its compliance range of 1.25 v to 0.10 v. refio can be driven by a single-supply amplifier or dac, thus allowing i ref to be varied for a fixed r set . since the input impedance of refio is approximately 1 m w , a simple, low cost r-2r ladder dac configured in the voltage mode topology may be used to control the gain. this circuit is shown in figure 20 using the ad7524 and an external 1.2 v reference, the ad1580. 1.2v 150pf +1.2v ref avdd reflo current source array avdd refio fs adj r set ad9752 i ref = v ref /r set avdd v ref v dd r fb out1 out2 agnd db7Cdb0 ad7524 ad1580 0.1v to 1.2v figure 20. single-supply gain control circuit
rev. 0 ad9752 C11C the second method may be used in a dual-supply system in which the common-mode voltage of refio is fixed and i ref is varied by an external voltage, v gc , applied to r set via an ampli- fier. an example of this method is shown in figure 21, in which the internal reference is used to set the common-mode voltage of the control amplifier to 1.20 v. the external voltage, v gc , is referenced to acom and should not exceed 1.2 v. the value of r set is such that i refmax and i refmin do not exceed 62.5 m a and 625 m a, respectively. the associated equations in figure 21 can be used to determine the value of r set . 150pf +1.2v ref avdd reflo current source array avdd refio fs adj r set ad9752 i ref v gc 1 m f i ref = (1.2Cv gc )/r set with v gc < v refio and 62.5 m a # i ref # 625a figure 21. dual-supply gain control circuit analog outputs the ad9752 produces two complementary current outputs, iouta and ioutb, which may be configured for single-end or differential operation. iouta and ioutb can be converted into complementary single-ended voltage outputs, v outa and v outb , via a load resistor, r load , as described in the dac transfer function section by equations 5 through 8. the differential voltage, v diff , existing between v outa and v outb can also be converted to a single-ended voltage via a transformer or differential amplifier configuration. figure 22 shows the equivalent analog output circuit of the ad9752 consisting of a parallel combination of pmos differen- tial current switches associated with each segmented current source. the output impedance of iouta and ioutb is deter- mined by the equivalent parallel combination of the pmos switches and is typically 100 k w in parallel with 5 pf. due to the nature of a pmos device, the output impedance is also slightly depe ndent on the output voltage (i.e., v outa and v outb ) and, to a lesser extent, the analog supply voltage, avdd, and full-scale current, i outfs . although the output impedances signal dependency can be a source of dc nonlinearity and ac linear- ity (i.e., distortion), its effects can be limited if certain precau- tions are noted. avdd ioutb iouta r load r load figure 22. equivalent analog output iouta and ioutb also have a negative and positive voltage compliance ran ge. the negative output compliance range of C1.0 v is set by the breakdown limits of the cmos process. operation beyond this maximum limit may result in a break- down of the output stage and affect the reliability of the ad9752. the positive output compliance range is slightly dependent on the full-scale output current, i outfs . it degrades slightly from its nominal 1.25 v for an i outfs = 20 ma to 1.00 v for an i outfs = 2 ma. operation beyond the positive compli ance range will induce clipping of the output signal which severely degrades the ad9752s linearity and distortion performance. for applications requiring the optimum dc linearity, iouta and/or ioutb should be maintained at a virtual ground via an i-v op amp configuration. maintaining iouta and/or ioutb at a virtual ground keeps the output impedance of the ad9752 fixed, signifi cantly reducing its effect on linearity. however, it does not necessarily lead to the optimum distortion perfor- mance due to limitations of the i-v op amp. note that the inl/dnl specifications for the ad9752 are measured in this manner using iouta. in addition, these dc linearity specifica tions remain virtually unaffected over the specified power supply range of 4.5 v to 5.5 v. operating the ad9752 with reduced voltage output swings at iouta and ioutb in a differential or single-ended output configuration reduces the signal dependency of its output impedance thus enhancing distortion performance. although the voltage compliance range of iouta and ioutb extends from C1.0 v to +1.25 v, optimum distortion performance is achieved when the maximum full-scale signal at iouta and ioutb does not exceed approximately 0.5 v. a properly se- lected transformer with a grounded center-tap will allow the ad9752 to provide the required power and voltage levels to different loads while maintaining reduced voltage swings at iouta and ioutb. dc-coupled applications requiring a differential or single-ended output configuration should size r load accordingly. refer to applying the ad9752 section for examples of various output configurations. the most significant improvement in the ad9752s distortion and noise performance is realized using a differential output configuration. the common-mode error sources of both iouta and ioutb can be substantially reduced by the common-mode rejection of a transformer or differential am- plifier. these common-mode error sources include even- order distortion products and noise. the enhancement in distortion performance becomes more significant as the recon- structed waveforms frequency content increases and/or its amplitude decreases. the distortion and noise performance of the ad9752 is also slightly dependent on the analog and digital supply as well as the full-scale current setting, i outfs . operating the analog supply at 5.0 v ensures maximum headroom for its internal pmos current sources and differential switches leading to improved distortion performance. although i outfs can be set between 2 ma and 20 ma, selecting an i outfs of 20 ma will provide the best dis- tortion and noise performance also shown in figure 8. the noise performance of the ad9752 is affected by the digital sup- ply (dvdd), output frequency, and increases with increasing clock rate as shown in figure 11. operating the ad9752 with low voltage logic levels between 3 v and 3.3 v will slightly re- duce the amount of on-chip digital noise.
rev. 0 ad9752 C12C in summary, the ad9752 achieves the optimum distortion and noise performance under the following conditions: (1) differential operation. (2) positive voltage swing at iouta and ioutb limited to +0.5 v. (3) i outfs set to 20 ma. (4) analog supply (avdd) set at 5.0 v. (5) digital supply (dvdd) set at 3.0 v to 3.3 v with appro- priate logic levels. note that the ac performance of the ad9752 is characterized under the above mentioned operating conditions. digital inputs the ad9752s digital input consists of 12 data input pins and a clock input pin. the 12-bit parallel data inputs follow standard positive binary coding where db11 is the most significant bit (msb) and db0 is the least significant bit (lsb). iouta produces a full-scale output current when all data bits are at logic 1. ioutb produces a complementary output with the full-scale current split between the two outputs as a function of the input code. the digital interface is implemented using an edge-triggered master slave latch. the dac output is updated following the rising edge of the clock as shown in figure 1 and is designed to support a clock rate as high as 125 msps. the clock can be operated at any duty cycle that meets the specified latch pulse- width. the setup and hold times can also be varied within the clock cycle as long as the specified minimum times are met; although the location of these transition edges may affect digital feedthrough and distortion performance. best performance is typically achieved when the input data transitions on the falling edge of a 50% duty cycle clock . the digital inputs are cmos compatible with logic thresholds, v threshold set to approximately half the digital positive supply (dvdd) or v threshold = dvdd /2 ( 20%) the internal digital circuitry of the ad9752 is capable of oper ating over a digital supply range of 2.7 v to 5.5 v. as a result, the digital inputs can also accommodate ttl levels when dvdd is set to accommodate the maximum high level voltage of the ttl drivers v oh(max) . a dvdd of 3 v to 3.3 v will typically ensure proper compatibility with most ttl logic families. figure 23 shows the equivalent digital input circuit for the data and clock inputs. the sleep mode input is similar with the exception that it contains an active pull-down circuit, thus ensuring that the ad9752 remains enabled if this input is left disconnected. dvdd digital input figure 23. equivalent digital input since the ad9752 is capable of being updated up to 125 msps, the quality of the clock and data input signals are important in achieving the optimum performance. the drivers of the digital data interface circuitry should be specified to meet the mini- mum setup and hold times of the ad9752 as well as its re- quired min/max input logic level thresholds. typically, the selection of the slowest logic family that satisfies the above con- ditions will result in the lowest data feedthrough and noise. digital signal paths should be kept short and run lengths matched to avoid propagation delay mismatch. the insertion of a low value resistor network (i.e., 20 w to 100 w ) between the ad9752 digital inputs and driver outputs may be helpful in reduc- ing any overshooting and ringing at the digital inputs that con- tribute to data feedthrough. for longer run lengths and high data update rates, strip line techniques with proper termination resis- tors should be considered to maintain clean digital inputs. also, operating the ad9752 with reduced logic swings and a corre- sponding digital supply (dvdd) will also reduce data feedthrough. the external clock driver circuitry should provide the ad9752 with a low jitter clock input meeting the min/max logic levels while providing fast edges. fast clock edges will help minimize any jitter that will manifest itself as phase noise on a recon- structed waveform. thus, the clock input should be driven by the fastest logic family suitable for the application. note, the clock input could also be driven via a sine wave, which is centered around the digital threshold (i.e., dvdd/2), and meets the min/max logic threshold. this will typically result in a slight degradation in the phase noise, which becomes more noticeable at higher sampling rates and output frequencies. also, at higher sampling rates, the 20% tolerance of the digital logic threshold should be considered since it will affect the effective clock duty cycle and subsequently cut into the required data setup and hold times. input clock/data timing relationship snr in a dac is dependent on the relationship between the position of the clock edges and the point in time at which the input data changes. the ad9752 is positive edge triggered, and so exhibits snr sensitivity when the data transition is close to this edge. in general, the goal when applying the ad9752 is to make the data transitions shortly after the positive clock edge. this becomes more important as the sample rate increases. figure 24 shows the relationship of snr to clock placement with dif- ferent sample rates and different frequencies out. note that at the lower sample rates, much more tolerance is allowed in clock placement, while at h igher rates, much more care must be taken. time of data change relative to rising clock edge C ns 68 40 C8 10 C6 C4 C2 0 2 4 6 8 64 60 56 52 48 snr C db 44 f s = 65msps f s = 125msps figure 24. snr vs. clock placement @ f out = 10 mhz
rev. 0 ad9752 C13C sleep mode operation the ad9752 has a power-down function which turns off the output current and reduces the supply current to less than 8.5 ma over the specified supply range of 2.7 v to 5.5 v and temperature range. this mode can be activated by applying a logic level 1 to the sleep pin. this digital input also con- tains an active pull-down circuit that ensures the ad9752 re- mains enabled if this input is left disconnected. the ad9752 takes less than 50 ns to power down and approximately 5 m s to power back up. power dissipation the power dissipation, p d , of the ad9752 is dependent on several factors which include: (1) avdd and dvdd, the power supply voltages; (2) i outfs , the full-scale current output; (3) f clock , the update rate; (4) and the reconstructed digital input waveform. the power dissipation is directly proportional to the analog supply current, i avdd , and the digital supply cur- rent, i dvdd . i avdd is directly proportional to i outfs as shown in figure 25 and is insensitive to f clock . conversely, i dvdd is dependent on both the digital input wave- form, f clock , and digital supply dvdd. figures 26 and 27 show i dvdd as a function of full-scale sine wave output ratios (f out /f clock ) for various update rates with dvdd = 5 v and dvdd = 3 v, respectively. note, how i dvdd is reduced by more than a factor of 2 when dvdd is reduced from 5 v to 3 v. i outfs C ma 35 5 220 4 6 8 1012 141618 30 25 20 15 10 i avdd C ma figure 25. i avdd vs. i outfs ratio (f clock /f out ) 18 16 0 0.01 1 0.1 i dvdd C ma 8 6 4 2 12 10 14 125msps 100msps 50msps 25msps 5msps figure 26. i dvdd vs. ratio @ dvdd = 5 v ratio (f clock /f out ) 8 0 0.01 1 0.1 i dvdd C ma 6 4 2 125msps 100msps 50msps 25msps 5msps figure 27. i dvdd vs. ratio @ dvdd = 3 v applying the ad9752 output configurations the following sections illustrate some typical output configura- tions for the ad9752. unless otherwise noted, it is assumed that i outfs is set to a nominal 20 ma. for applications requir- ing the optimum dynamic performance, a differential output configuration is suggested. a differential output configuration may consist of either an rf transformer or a differential op amp configuration. the transformer configuration provides the opti- mum high frequency performance and is recommended for any application allowing for ac coupling. the differential op amp configuration is suitable for applications requiring dc coupling, a bipolar output, signal gain and/or level shifting. a single-ended output is suitable for applications requiring a unipolar voltage output. a positive unipolar output voltage will result if iouta and/or ioutb is connected to an appropri- ately sized load resistor, r load , referred to acom. this con- figuration may be more suitable for a single-supply system requiring a dc coupled, ground referred output voltage. alterna- tively, an amplifier could be configured as an i-v converter thus converting iouta or ioutb into a negative unipolar voltage. this configuration provides the best dc linearity since iouta or ioutb is maintained at a virtual ground. note, iouta provides slightly better performance than ioutb. differential coupling using a transformer an rf transformer can be used to perform a differential-to- single-ended signal conversion as shown in figure 28. a differentially coupled transformer output provides the optimum distortion performance for output signals whose spectral content lies within the transformers passband. an rf transformer such as the mini-circ uits t1-1t provides exc ellent rejection of common-mode distortion (i.e., even-order harmonics) and noise over a wide frequency range. it also provides electrical isolation and the ability to deliver twice the power to the load. trans- formers with different impedance ratios may also be used for impedance matching purposes. note that the transformer provides ac coupling only.
rev. 0 ad9752 C14C r load ad9752 mini-circuits t1-1t optional r diff iouta ioutb figure 28. differential output using a transformer the center tap on the primary side of the transformer must be connected to acom to provide the necessary dc current path for both iouta and ioutb. the complementary voltages appearing at iouta and ioutb (i.e., v outa and v outb ) swing symmetrically around acom and should be maintained with the specified output compliance range of the ad9752. a differential resistor, r diff , may be inserted in applications in which the output of the transformer is connected to the load, r load , via a passive reconstruction filter or cable. r diff is deter- mined by the transformers impedance ratio and provides the proper source termination which results in a low vswr. note that approximately half the signal power will be dissipated across r diff . differential using an op amp an op amp can also be used to perform a differential to single- ended conversion as shown in figure 29. the ad9752 is con- figured with two equal load resistors, r load , of 25 w . the differential voltage developed across iouta and ioutb is converted to a single-ended signal via the differential op amp configuration. an optional capacitor can be installed across iouta and ioutb forming a real pole in a low-pass filter. the addition of this capacitor also enhances the op amps distor- tion performance by preventing the dacs high slewing output from overloading the op amps input. ad9752 iouta ioutb c opt 500 v 225 v 225 v 500 v 25 v 25 v ad8055 figure 29. dc differential coupling using an op amp the common-mode rejection of this configuration is typically determined by the resistor matching. in this circuit, the differ- ential op amp circuit is configured to provide some additional signal gain. the op amp must operate off of a dual supply since its output is approximately 1.0 v. a high speed amplifier such as the ad8055 or ad9632 capable of preserving the differential performance of the ad9752 while meeting other system level object ives (i.e., cost, power) should be selected. the op amps differential gain, its gain setting resistor values, and full-scale output swing capabilities should all be considered when opti- mizing this circuit. the differential circuit shown in figure 30 provides the neces- sary level-shifting required in a single supply system. in this case, avdd which is the positive analog supply for both the ad9752 and the op amp is also used to level-shift the differ- ential output of the ad9752 to midsupply (i.e., avdd/2). the ad8041 is a suitable op amp for this application. ad9752 iouta ioutb c opt 500 v 225 v 225 v 1k v 25 v 25 v ad8041 1k v avdd figure 30. single-supply dc differential coupled circuit single-ended unbuffered voltage output figure 31 shows the ad9752 configured to provide a unipolar output range of approximately 0 v to +0.5 v for a doubly termi- nated 50 w cable since the nominal full-scale current, i outfs , of 20 ma flows through the equivalent r load of 25 w . in this case, r load represents the equivalent load resistance seen by iouta or ioutb. the unused output (iouta or ioutb) can be connected to acom directly or via a matching r load . different values of i outfs and r load can be selected as long as the positive compliance range is adhered to. one additional consideration in this mode is the integral nonlinearity (inl) as discussed in the analog output section of this data sheet. for optimum inl performance, the single-ended, buffered voltage output configuration is suggested. ad9752 iouta ioutb 50 v 25 v 50 v v outa = 0 to +0.5v i outfs = 20ma figure 31. 0 v to +0.5 v unbuffered voltage output single-ended, buffered voltage output configuration figure 32 shows a buffered single-ended output configuration in which the op amp u1 performs an i-v conversion on the ad9752 output current. u1 maintains iouta (or ioutb) at a virtual ground, thus minimizing the nonlinear output impedance effect on the dacs inl performance as discussed in the analog output section. although this single-ended configuration typically provides the best dc linearity performance, its ac distor- tion performance at higher dac update rates may be limited by u1s slewing capabilities. u1 provides a negative unipolar out- put vo ltage and its full-scale output voltage is simply the product of r fb and i outfs . the full-scale output should be set within u1s voltage output swing capabilities by scaling i outfs and/or r fb . an improvement in ac distortion performance may result with a reduced i outfs since the signal current u1 will be required to sink will be subsequently reduced.
rev. 0 ad9752 C15C ad9752 iouta ioutb c opt 200 v u1 v out = i outfs 3 r fb i outfs = 10ma r fb 200 v figure 32. unipolar buffered voltage output power and grounding considerations, power supply rejection many applications seek high speed and high performance under less than ideal operating conditions. in these circuits, the imple- mentation and construction of the printed circuit board design is as important as the circuit design. proper rf techniques must be used for device selection, placement and routing as well as power supply bypassing and grounding to ensure optimum performance. figures 42-47 illustrate the recommended printed circuit board ground, power and signal plane layouts which are implemented on the ad9752 evaluation board. one factor that can measurably affect system performance is the ability of the dac output to reject dc variations or ac noise superimposed on the analog or digital dc power distribution (i.e., avdd, dvdd). this is referred to as power supply rejection ratio (psrr). for dc variations of the power supply, the resulting performance of the dac directly corresponds to a gain error associated with the dacs full-scale current, i outfs . ac noise on the dc supplies is common in applications where the power distribution is generated by a switching power supply. typically, switching power supply noise will occur over the spectrum from tens of khz to several mhz. psrr vs. frequency of the ad9752 avdd supply, over this frequency range, is given in figure 33. frequency C mhz 90 80 60 1.0 0.26 psrr C db 0.5 0.75 70 figure 33. power supply rejection ratio of ad9752 note that the units in figure 33 are given in units of (amps out)/ (volts in). noise on the analog power supply has the effect of modulating the internal switches, and therefore the output current. the voltage noise on the dc power, therefore, will be added in a nonlinear manner to the desired i out . due to the rela tive different sizes of these switches, psrr is very code depen- dent. this can produce a mixing effect which can modu late low frequency power supply noise to higher frequencies. worst case psrr for either one of the differential dac outputs will occur when the full-scale current is directed towards that output. as a result, the psrr measurement in figure 33 represents a worst case condition in which the digital inputs remain static and the full scale output current of 20 ma is directed to the dac out- put being measured. an example serves to illustrate the effect of supply noise on the analog supply. suppose a switching regulator with a switching frequency of 250 khz produces 10 mv rms of noise and for simplicity sake (i.e., ignore harmonics), all of this noise is con- centrated at 250 khz. to calculate how much of this undesired noise will appear as current noise super imposed on the dacs full-scale current, i outfs , one must determine the psrr in db using figure 33 at 250 khz. to calculate the psrr for a given r load , such that the units of psrr are converted from a/v to v/v, adjust the curve in figure 33 by the scaling factor 20 log (r load ). for instance, if r load is 50 w , the psrr is re duced by 34 db (i.e., psrr of the dac at 1 mhz which is 74 db in figure 33 becomes 40 db v out /v in ). proper grounding and decoupling should be a primary objective in any high speed, high resolution system. the ad9752 features separate analog and digital supply and ground pins to optimize the management of analog and digital ground currents in a system. in general, avdd, the analog supply, should be de- coupled to acom, the analog common, as close to the chip as physically possible. similarly, dvdd, the digital supply, sh ould be decoupled to dcom as close as physically as possible. for those applications that require a single +5 v or +3 v supply for both the analog and digital supply, a clean analog supply may be generated using the circuit shown in figure 34. the circuit consists of a differential lc filter with separate power supply and return lines. lower noise can be attained using low esr type electrolytic and tantalum capacitors. 100 m f elect. 10-22 m f tant. 0.1 m f cer. ttl/cmos logic circuits +5v or +3v power supply ferrite beads avdd acom figure 34. differential lc filter for single +5 v or +3 v applications maintaining low noise on power supplies and ground is critical to obtaining optimum results from the ad9752. if properly implemented, ground planes can perform a host of functions on high speed circuit boards: bypassing, shielding, current trans- port, etc. in mixed signal design, the analog and digital portions of the board should be distinct from each other, with the analog ground plane confined to the areas covering the analog signal traces, and the digital ground plane confined to areas covering the digital interconnects. all analog ground pins of the dac, reference and other analog components should be tied directly to the analog ground plane. the two ground planes should be connected by a path 1/8 to 1/4 inch wide underneath or within 1/2 inch of the dac to
rev. 0 ad9752 C16C maintain optimum performance. care should be taken to ensure that the ground plane is uninterrupted over crucial signal paths. on the digital side, this includes the digital input lines running to the dac as well as any clock signals. on the analog side, this includes the dac output signal, reference signal and the supply feeders. the use of wide runs or planes in the routing of power lines is also recommended. this serves the dual role of providing a low series impedance power supply to the part, as well as providing some free capacitive decoupling to the appropriate ground plane. it is essential that care be taken in the layout of signal and power ground interconnects to avoid inducing extraneous volt- age drops in the signal ground paths. it is recommended that all connections be short, direct and as physically close to the pack- age as possible in order to minimize the sharing of conduction paths between different currents. when runs exceed an inch in length, strip line techniques with proper termination resistor should be considered. the necessity and value of this resistor will be dependent upon the logic family used. for a more detailed di scussion of the implementation and construction of high speed, mixed signal printed circuit boards, refer to analog devices application notes an-280 and an-333. frequency C hz C30 C40 C100 1m 600k amplitude C dbm 800k C50 C60 C70 C80 C90 figure 35a. notch in missing bin at 750 khz is down >60 db. (peak amplitude + 0 dbm). frequency C mhz C30 C40 C100 5.15 4.85 amplitude C dbm 5 C50 C60 C70 C80 C90 C110 figure 35b. notch in missing bin at 5 mhz is down >60 db. (peak amplitude + 0 dbm). applications vdsl applications using the ad9752 very high frequency digital subscriber line (vdsl) technol- ogy is growing rapidly in applications requiring data transfer over relatively short distances. by using qam modulation and transmitting the data in multiple discrete tones, high data rates can be achieved. as with other multitone applications, each vdsl tone is ca- pable of transmitting a given number of bits, depending on the signal-to-noise ratio (snr) in a narrow band around that tone. the tones are evenly spaced over the range of several khz to 10 mhz. at the high frequency end of this range, performance is generally limited by cable characteristics and environmental factors, such as external interferers. performance at the lower frequencies is much more dependent on the performance of the components in the signal chain. in addition to in-band noise, intermodulation from other tones can also potentially interfere with the recovery of data for a given tone. the two graphs in figure 35 represent a 500 tone missing bin test vector, with frequencies evenly spaced from 400 hz to 10 mhz. this test is very commonly done to determine if distortion will limit the number of bits which can be transmitted in a tone. the test vector has a series of missing tones around 750 khz, which is represented in figure 35a and a series of missing tones around 5 mhz which is represented in figure 35b. in both cases, the spurious free range between the transmitted tones and the empty bins is greater than 60 db. using the ad9752 for quadrature amplitude modulation (qam) qam is one of the most widely used digital modulation schemes in digital communication systems. this modulation technique can be found in fdm as well as spreadspectrum (i.e., cdma) based systems. a qam signal is a carrier frequency that is modulated in both amplitude (i.e., am modulation) and phase (i.e., pm modulation). it can be generated by indepen- dently modulating two carriers of identical frequency but with a 90 phase difference. this results in an in-phase (i) carrier com- ponent and a quadrature (q) carrier component at a 90 phase shift with respect to the i component. the i and q components are then summed to provide a qam signal at the specified car- rier frequency. a common and traditional implementation of a qam modu- lator is shown in figure 36. the modulation is performed in the analog domain in which two dacs are used to generate the baseband i and q components, respectively. each component is then typically applied to a nyquist filter before being applied to a quadrature mixer. the matching nyquist filters shape and limit each components spectral envelope while minimizing intersymbol interference. the dac is typically updated at the qam symbol rate or possibly a multiple of it if an interpolating filter precedes the dac. the use of an interpolating filter typi- cally eases the implementation and complexity of the analog filter, which can be a significant contributor to mismatches in gain and phase between the two baseband channels. a quadra- ture mixer modulates the i and q components with in-phase and quadrature phase carrier frequency and then sums the two outputs to provide the qam signal.
rev. 0 ad9752 C17C ad9752 (i dac) ad9752 (q dac) iouta ioutb qouta qoutb dcom fsadj refio sleep r set2 1.9k v 0.1 m f clk q data input i data input dvdd avdd 100w 500 v 100 v c filter 100 v c filter 100 v 500 v 500 v 500 v 500 v 500 v 500 v 634 v 0.1 m f +5v vpbf bbip bbin bbqp bbqn ad8346 phase splitter loip loin vout 500mv p-p with v cm =1.2v note: 500 v resistor network - ohmtek orn5000d 100 v resistor network - tomc1603-100d reflo acom reflo avdd refio fsadj r set1 2k v r cal 220 v u1 u2 avdd 1.82v latches 500 v dac dac + latches figure 37. baseband qam implementation using two ad9752s ad9752 0 90 ad9752 carrier frequency 12 12 to mixer dsp or asic nyquist filters quadrature modulator s figure 36. typical analog qam architecture in this implementation, it is much more difficult to maintain proper gain and phase matching between the i and q channels. the circuit implementation shown in figure 37 helps improve upon the matching and temperature stability characteristics between the i and q channels, as well as showing a path for up- conversion using the ad8346 quadrature modulator. using a single voltage reference derived from u1 to set the gain for both the i and q channels will improve the gain matching and stabil- ity. r cal can be used to compensate for any mismatch in gain between the two channels. this mismatch may be attributed to the mismatch between r set1 and r set2 , effective load resistance of each channel, and/or the voltage offset of the control ampli- fier in each dac. the differential voltage outputs of u1 and u2 are fed into the respective differential inputs of the ad8346 via matching networks. using the same matching techniques described above, figure 38 shows an example of the ad9752 used in a w-cdma transmit- ter application using the ad6122 cdma 3 v transmitter if subsystem. the ad6122 has functions, such as external gain control and low distortion characteristics, needed for the supe- rior adjacent channel power (acp) requirements of w-cdma. cdma carrier division multiple access, or cdma, is an air transmit/ receive scheme where the signal in the transmit path is modu- lated with a pseudorandom digital code (sometimes referred to as the spreading code). the effect of this is to spread the trans- mitted signal across a wide spectrum. similar to a dmt wave- form, a cdma waveform containing multiple subscribers can be characterized as having a high peak to average ratio (i.e., crest factor), thus demanding highly linear components in the transmit signal path. the bandwidth of the spectrum is defined by the cdma standard being used, and in operation is imple- mented by using a spreading code with particular characteristics. distortion in the transmit path can lead to power being trans- mitted out of the defined band. the ratio of power transmitted in-band to out-of-band is often referred to as adjacent channel power (acp). this is a regulatory issue due to the possibility of interference with other signals being transmitted by air. regula- tory bodies define a spectral mask outside of the transmit band, and the acp must fall under this mask. if distortion in the transmit path cause the acp to be above the spectral mask, then filtering, or different component selection is needed to meet the mask requirements.
rev. 0 ad9752 C18C ad9752 (i dac) ad9752 (q dac) iouta ioutb qouta qoutb dcom fsadj refio sleep r set2 1.9k v 0.1 m f clk q data input i data input dvdd avdd 100w 500 v 100 v c filter 100 v 500 v 500 v 500 v 500 v 500 v 500 v 634 v +3v iipp iipn iiqp iiqn ad6122 reflo acom reflo avdd refio fsadj r set1 2k v r cal 220 v u1 u2 avdd latches 500 v dac dac latches 100 v phase splitter 4 2 temperature compensation gain control scale factor refin vgain gain control loipp loipn txopp txopn v cc v cc figure 38. cdma transmit application using ad9752 figure 39 shows the ad9752 reconstructing a wideband, or w-cdma test vector with a bandwidth of 5 mhz, centered at 15.625 mhz and being sampled at 62.5 msps. acp for the given test vector is measured at 70 db. C20 C80 C120 center 16.384mhz span 14.096mhz 1.4096mhz C30 C70 C90 C110 C50 C60 C100 C40 co co cl1 cu1 figure 39. cdma signal, sampled at 65 msps, adjacent channel power >70 dbm it is also possible to generate a qam signal completely in the digital domain via a dsp or asic, in which case only a single dac of sufficient resolution and performance is required to reconstruct the qam signal. also available from several vendors are digital asics which implement other digital modulation schemes such as psk and fsk. this digital implementation has the benefit of generating perfectly matched i and q components in terms of gain and phase, which is essential in maintaining optimum performance in a communication system. in this imple- mentation, the reconstruction dac must be operating at a sufficiently high clock rate to accommodate the highest specified qam carrier frequency. figure 40 shows a block diagram of such an implementation using the ad9752. 50 v ad9752 lpf 50 v to mixer stel-1130 qam 12 cos 12 sin 12 12 i data q data 12 carrier frequency 12 stel-1177 nco clock figure 40. digital qam architecture ad9752 evaluation board general description the AD9752-EB is an evaluation board for the ad9752 12-bit d/a converter. careful attention to layout and circuit design combined with a prototyping area allow the user to easily and effectively evaluate the ad9752 in any application where high resolution, high speed conversion is required. this board allows the user the flexibility to operate the ad9752 in various configurations. possible output configurations include transformer coupled, resistor terminated, inverting/noninverting and differential amplifier outputs. the digital inputs are designed to be driven directly from various word generators, with the on-board option to add a resistor network for proper load termination. provisions are also made to operate the ad9752 with either the internal or ext ernal reference, or to exercise the power-down feature. refer to the application note an-420 for a thorough description and operating instructions for the ad9752 evaluation board.
rev. 0 ad9752 C19C 1098765432 1 r4 10 9 8 7 6 5 4 3 2 1 r7 dvdd 10 9 8 7 6 5 4 3 2 1 r3 1098765432 1 dvdd r6 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 p1 10 9 8 7 6 5 4 3 2 1 r5 dvdd 10 9 8 7 6 5 4 3 2 1 r1 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 c19 c1 c2 c25 c26 c27 c28 c29 16 pindip res pk 16 15 14 13 12 11 10 1 2 3 4 5 6 7 c30 c31 c32 c33 c34 c35 c36 16 pindip res pk 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 db13 db12 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 clock dvdd dcom nc avdd comp2 iouta ioutb acom comp1 fs adj refio reflo sleep u1 ad975x avdd ct1 a 1 a r15 49.9 v clk jp1 ab 3 2 1 j1 tp1 extclk c7 1 m f c8 0.1 m f avdd a c9 0.1 m f tp8 2 avdd tp11 c11 0.1 m f tp10 tp9 r16 2k v tp14 jp4 c10 0.1 m f out 1 out 2 tp13 r17 49.9 v pdin j2 a a a avdd 3 jp2 tp12 tp7 a c6 10 m f avcc b6 tp6 a c5 10 m f avee b5 tp19 a agnd b4 tp18 tp5 c4 10 m f tp4 avdd b3 tp2 dgnd b2 c3 10 m f tp3 dvdd b1 r20 49.9 v j3 c12 22pf a a r14 0 a 4 5 6 1 3 t1 j7 r38 49.9 v j4 a a jp6a jp6b a r13 open c13 22pf c20 0 r12 open a b a jp7b b a jp7a r10 1k v b a jp8 r9 1k v a b a r35 1k v jp9 r18 1k v a 3 7 6 2 4 ad8047 c21 0.1 m f a c22 1 m f r36 1k v c23 0.1 m f a c24 1 m f avee avcc r37 49.9 v j6 a 3 7 6 2 4 1 2 3 jp5 c15 0.1 m f a avee r46 1k v c17 0.1 m f a 1 2 3 jp3 a b avcc a cw r43 5k v r45 1k v c14 1 m f a r44 50 v extrefin j5 a r42 1k v c16 1 m f a avcc c18 0.1 m f u7 6 2 4 a vin vout gnd ref43 98765432 1 r2 10 a 1098765432 1 dvdd r8 u6 a ad8047 out2 out1 u4 figure 41. evaluation board schematic
rev. 0 ad9752 C20C figure 42. silkscreen layertop figure 43. component side pcb layout (layer 1)
rev. 0 ad9752 C21C figure 44. ground plane pcb layout (layer 2) figure 45. power plane pcb layout (layer 3)
rev. 0 ad9752 C22C figure 46. solder side pcb layout (layer 4) figure 47. silkscreen layerbottom
rev. 0 ad9752 C23C 28-lead, 300 mil soic (r-28) seating plane 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.0500 (1.27) bsc 0.0125 (0.32) 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 8 8 0 8 0.0291 (0.74) 0.0098 (0.25) 3 45 8 0.7125 (18.10) 0.6969 (17.70) 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) pin 1 28 15 14 1 28-lead tssop (ru-28) 28 15 14 1 0.386 (9.80) 0.378 (9.60) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 0.169 (4.30) pin 1 seating plane 0.006 (0.15) 0.002 (0.05) 0.0118 (0.30) 0.0075 (0.19) 0.0256 (0.65) bsc 0.0433 (1.10) max 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) 8 8 0 8 outline dimensions dimensions shown in inches and (mm). c3332C8C1/99 printed in u.s.a.

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